System and method for heating and cooling wafer at accelerated rates

ABSTRACT

A highly dynamic heating and/or chilling chamber for processing semiconductor wafers. The chamber has uniform heat and gas flow distribution in order to minimize the temperature gradient at different points of the wafer.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductorprocessing, and relates more specifically to the heating and cooling ofwafers used to make integrated circuits.

[0003] 2. Related Art

[0004] Microelectronic devices are fabricated employing multiple layersof materials formed upon suitable carriers or substrates. Many of thelayers of microelectronics materials must be patterned and registeredaccurately to produce fine dimensions. As circuit density andperformance requirements have increased, the tolerances and dimensionsof the patterns have become correspondingly smaller. It is commonpractice to form patterns in layers of microelectronic materialsemploying photolithography, wherein the layer of material to bepatterned is coated with a light sensitive lacquer or photoresistmaterial, which is then exposed to a pattern of light radiation to formthe latent image of the pattern in the photoresist material. This latentimage is then chemically developed to form a photoresist etch mask ofthe pattern, which can then be transferred to the underlying materiallayer by additive or subtractive processes such as etching or otheranalogous processes.

[0005] As feature sizes in the production of integrated circuitsapproach 100 nm, problems of packing density become increasinglydifficult to overcome. The major problem is lithographic exposure toolresolution for exposure of photoresists. Photoresists and themanipulation of photoresists are well known in the art, but a shortdescription of some important issues follows. Photoresists are appliedas a thin film coating to a suitable substrate. Upon imagewise exposureof the coated substrate to actinic radiation, the difference insolubility rates between exposed and unexposed areas produces an imageon the substrate after development. The uncovered substrate isthereafter subjected to an etching process. Frequently, this involves aplasma etching against which the resist coating must be sufficientlystable. For a positive tone photoresist, the coating protects thoseareas of the substrate from the etchant which were covered during theexposure, and thus the etchant is only able to etch the areas which wereuncovered. The photoresist coating protects the covered areas of thesubstrate from the etchant and thus the etchant is only able to etch theuncovered areas of the substrate. Thus, a pattern can be created on thesubstrate which corresponds to the pattern of the mask or template thatwas used to create selective exposure patterns on the coated substrateprior to development.

[0006] The ability to reproduce very small dimensions, is extremelyimportant in the production of large scale integrated circuits onsilicon chips and similar components. As the integration degree ofsemiconductor devices becomes higher, finer photoresist film patternsare required. One way to increase circuit density on such a chip is byincreasing the resolution capabilities of the resist.

[0007] The optimally obtainable microlithographic resolution isessentially determined by the radiation wavelengths used for theselective irradiation. However the resolution capacity that can beobtained with conventional deep UV microlithography (i.e. 248 nm) hasits limits. In order to be able to sufficiently resolve optically smallstructural elements, e.g. features of 0.13 microns and smaller,radiation of ever shorter wavelengths (particularly 193 nm) is beingemployed together with chemical amplification resist films.

[0008] A typical chemical amplification photoresist film comprises apolymer, a photoacid generator, and other optional additives. Thepolymer is required to be soluble in the chosen developer solution, andhave high thermal stability and low absorbtance to the exposurewavelength in addition to having excellent etch resistance. Chemicallyamplified photoresists are based on chemically amplified deblocking.With this mechanism, a molecule of photogenerated acid catalyzes thebreaking of bonds in a protecting group of a polymer. During thedeblocking process, another molecule of the same acid is created as abyproduct, and continues the acid-catalytic deblocking cycle.

[0009] Chemically amplified resists require both an exposure dose togenerate a latent acid and image and a thermal dose to drive thedeblocking reaction that changes the solubility of the resist indeveloper. Because the photogenerated acid diffuses through the resistas it catalyzes the deblocking reaction, the acid could diffuse intounexposed regions and have a significant impact on the quality of theimage generated in the resist. An important criteria of thepost-exposure bake process (PEB) is optimization of the balance betweenthe relative rates of the diffusion and reaction processes. Prediffusion reaction processes may include photo acid loss to theenvironment. The post diffusion reaction processes are morespecifically, the amplification reaction and the acid loss reaction.Because the diffusivity and the reaction rate are both temperaturedependent, careful manipulation and monitoring of the thermal history ofthe resist is critical to the final dimensions of the integratedcircuit. The diffusion process, the amplification reaction process, andthe acid loss reaction each have different activation energies. Theactivation energies for diffusion and for the amplification reaction areboth high, whereas the activation energy for the acid loss reaction islow in comparison.

[0010] Because of this, the ramp or rise time is critical in theformation of dense features. Lines or other features that are denselylocated may join together in a process known as scumming, whereasisolated lines or features exposed to the same thermal dose willincrease linearly and be well resolved. At the beginning of the bake,the acid loss reaction scavenges acid before the wafer reaches atemperature that is hot enough to drive the deblocking reaction. Afterthe hotplate temperature is reached, acid loss, diffusion andamplification occur simultaneously. Delays in reaching the baketemperature can result in substantial acid loss before deblocking canbegin, contributing to the aforementioned scumming process. For moreinformation please refer to an article by Mark D. Smith which is herebyincorporated by reference in its entirety, entitled “Modeling the impactof thermal history during post exposure bake on the lithographicperformance of chemically amplified resists,” proceeding of SPIE, Vol.4345, 1013-1021, 2001, Advances in Resist Technology and ProcessingXVIII.

[0011] FIGS. 1-3 illustrate a prior art oven used for post-exposurebaking of silicon wafers. FIG. 1 is an exploded view of a prior art ovenillustrating a top enclosure 20, gas inlet 22, showerhead 24, wafer 28,hot plate 32 with proximity pins 34, lift off pins 36 and bottomenclosure 40. FIG. 2 is a cross section of the prior art oven shown inFIG. 1 in the open position, with wafer 28 elevated from the surface ofhotplate 32 and proximity pins 34. FIG. 3 is a cross section of theprior art oven shown in FIG. 1 in a closed potion, with the wafer 28upon proximity pins 34 of hot plate 32. Showerhead 24 has passages todistribute the gas arriving from gas inlet 22. One example of such anoven is manufactured by Tokyo Electron Corporation (TEC) of Kumamoto,Japan.

[0012] Generally the proximity pins raise wafer 28 about 100-150 micronsoff of the surface of hot plate 32. In practice, wafer 28 cannot be madeor maintained during prior processing perfectly flat, and there aredifferences in the degree of flatness from wafer to wafer. Because ofthe vertical temperature gradient within the oven, even small variationsin flatness can result in a relatively large disparity in thetemperature at different points across wafer 28. For example, if thewafer is concave such that the ends are further from hotplate 32 thanthe middle, the middle portion will be hotter than the ends. Thisvariation may result in a rise time that differs by a factor of two atdifferent areas of the wafer in the prior art design, and is thusdetrimental to precision activation and control of the diffusion andreaction processes.

SUMMARY

[0013] One aspect of the present invention is a system for varying thetemperature of a wafer comprising a first temperature controlled plate.A second temperature controlled plate has proximity pins, and the waferis located between the first and second temperature controlled plates.The distance of the wafer from the first temperature controlled plate ismaintained by proximity pins. The distance of the wafer from the secondtemperature controlled plate can be maintained in any number of ways butis preferably maintained by the proximity pins of the second hot plate.An enclosure surrounds the first and second temperature controlledplates and the wafer, and the enclosure comprises a gas input andoutput. A heat conducting gas flows from the input past the wafer and tothe output.

[0014] Another aspect of the present invention involves a method ofconditioning a wafer having a first and a second side within a chamber.The method comprises heating or cooling the wafer from the first side,heating or cooling the wafer from the second side, and applying a gas tothe wafer, the gas distributed through a plurality of passages such thatthe gas flow is controlled and is substantially laminar and spatiallydistributed.

[0015] Yet another aspect of the invention is a device for controllingthe temperature of a wafer comprising a temperature control element, anda gas distribution system configured to distribute gas about a surfaceof the wafer, the gas distribution system comprising a plurality of flowpaths, each of the plurality of flow paths comprising a laminar flowelement. Within the device a wafer is located between the gasdistribution system and the temperature control element.

[0016] Other aspects and advantages of the present invention will becomeapparent from the following descriptions and accompanying drawings

BRIEF DESCRIPTION OF THE FIGURES

[0017] The present invention may be better understood, and its numerousfeatures and advantages made apparent by referencing the accompanyingfigures. For simplicity and ease of understanding, common numbering ofelements within the illustrations is employed where an element is thesame in different figures.

[0018]FIG. 1 is an exploded view of a prior art oven.

[0019]FIG. 2 is a cross section of the oven shown in FIG. 1.

[0020]FIG. 3 is a cross section of the oven shown in FIG. 1.

[0021]FIG. 4 is an exploded view of semiconductor processing chamber(“SPC”) 100.

[0022]FIG. 5 is a perspective view of flow channel plate 112.

[0023]FIG. 6 is a cross section of SPC 100 in an open position.

[0024]FIG. 7 is a cross section of SPC 100 in a closed position.

[0025]FIG. 8 is a cross section of SPC 100 in a closed position.

DETAILED DESCRIPTION

[0026] The following is a detailed description of illustrativeembodiments of the present invention. As these embodiments of thepresent invention are described with reference to the aforementioneddrawings, various modifications or adaptations of the methods and orspecific structures described may become apparent to those skilled inthe art. All such modifications, adaptations, or variations that relyupon the teachings of the present invention, and through which theseteachings have advanced the art, are considered to be within the scopeof the present invention. Hence, these descriptions and drawings are notto be considered in a limiting sense, as it is understood that thepresent invention is in no way limited to the embodiments illustrated.

[0027]FIG. 4 illustrates an exploded view of semiconductor processingchamber (“SPC”) 100. SPC 100 may be used to heat or cool a silicon waferor other substrate in addition to supplying other process needs such asgas distribution and vapor removal. SPC 100 has many applications in thefield of silicon wafer processing. One such application is in thepost-exposure bake process described earlier. Other applications will bereadily apparent to those skilled in the art.

[0028] Silicon wafer 126 is conditioned within upper housing 104 andlower housing 134. Although SPC 100 may be used to cool the wafer aswell as heat it and condition it in other ways, it may be referred to asan oven.

[0029] Mechanical assembly 102 drives the opening and closing of SPC100, i.e. it brings together or separates the upper housing 104 andlower housing 134 to close or open SPC 100. Gas transport tubes 106 aand 106 b are attached to upper housing 104 and cover plate 110respectively. Gas transport tubes 106 route an incoming gas used in theconditioning process to flow manifold 111 which is formed by cover plate110 and flow channel plate 112. Gas flows through manifold 111 throughupper hot (or chill) plate 124 which functions as part of a gasdistribution system. The gas applied is generally nitrogen but the gasdistribution system can, of course, transport any gas to wafer 126.Springs 108 compress the various components of SPC 100 while allowingfreedom of movement and size variations of the various components,including wafer 126.

[0030] Wafer 126 is supported on lower hot (or chill) plate 132 byproximity pins 133. Proximity pins 133 are positioned to keep wafer 126uniformly distanced from the upper surface of lower hot plate 132. Theymay be concentrically arranged or arranged in any other pattern upon thesurface of lower hot plate 132 to minimize warping of the wafer duringthe heating, cooling, and conditioning processes. Precise positioning ofthe wafer 126 is critical in order to uniformly heat, cool, or otherwisecondition wafer 126. Misalignment or improper distancing of wafer 126from either lower hot plate 132 or upper hot plate 124 would subjectdifferent areas of wafer 126 to different temperature profiles orgradients. Even minimal differences in the temperature profile that awafer may be subjected to during the conditioning process can have majoreffects on the line width and circuit formation of integrated circuitsbeing formed on/in wafer 126. In the case where hot plate 132 is used toheat the wafer, it has electrical heating elements embedded within it.In the case that hot plate 132 is used as a chill plate to cool thewafer, a thermoelectric cooler or any other well known means such ascool liquid passages may be employed. Thus the term hot plate is definedas a temperature controlling plate that may either heat or cool itssurroundings.

[0031] Lift pin assembly 130 is used to place wafer 126 on the proximitypins 133 when the wafer is inserted and also to lift wafer 126 from theproximity pins 133 when the wafer is removed from SPC 100.

[0032] Exhaust ring 128 restricts and controls the flow of exhaustexiting from the edge of hot plate 132 within SPC 100. Different levelsof exhaust restriction can be tailored for different processingapplications. Exhaust ring 128 assures uniformity of flow around theannular exhaust opening formed between exhausting 128 and hot plate 132.With the input and exhaust rate controlled, SPC 100 provides for radialadjustment and control of the gas flow rate over the surface of wafer126. Distribution of the gas will now be described in further detailwith regard to FIG. 5.

[0033]FIG. 5 shows flow channel plate (“FCP”) 112 of manifold 111. Coverplate 110 (not shown) seals against the topside of FCP 112.Specifically, cover plate 110 makes direct contact with seal ring 113and planar contact area 122. Alternatively, an additional gasket can beincluded between FCP 112 and cover plate 110. Gas arrives from gastransport tubes 106 through cover plate 110 into an annular channelformed by distribution ring 114, which is a recessed portion of FCP 112,and cover plate 110. FCP 112 is preferably formed by etching a piece ofmetal, or metal foil, although many other well know metal-workingmethods may be employed. Additionally, although a metal such as nickelor stainless steel is preferred in order to avoid contamination of thewafer, any other material known in the art may be employed to formmanifold 111. Distribution ring 114 is recessed relative to seal ring113. Gas flows through the annular channel above distribution ring 114through various distribution channels 116 to different areas of thesurface of wafer 126 (not shown). Annular channel 114 ranges from 2 mmto 2 cm in width and from 0.2 mm to 5 mm in depth. Distribution channels116 each have a feed passage 117 and a laminar flow passage (“LFP”) 118.The laminar flow passages 118 assure constant and evenly distributedflow upon the surface of the wafer. The LFPs 118 are tailored tooptimize the flow distribution for a range of applications. Generallyspeaking, the depth of distribution channels 116 may range from about 50microns to about 800 microns and is preferably 150 microns. For moreinformation on laminar flow passages please refer to U.S. Pat. No.4,685,331 to Renken et al., entitled “Thermal Mass Flow Meter andController,” which is hereby incorporated by this reference in itsentirety. Feed passages 117 transport the gas from distribution ring 114to LFPs 118. At the end of each distribution channel is gas deliverycavity 120. Each gas delivery cavity 120 is aligned with a gas passagethrough upper hot plate 124.

[0034] Any solvents or contaminants that are present within SPC 100, forinstance those that may originate or evaporate from wafer 126 during thepost-exposure bake and travel through the passages in upper hot plate124, will condense and/or accumulate in gas delivery cavities 120. Thus,gas delivery cavities 120, which are fabricated to a much greater depththan the laminar flow passages to accommodate condensed contaminatesprotect laminar flow passages 118 from contaminants and any resultantclogging or flow impediment.

[0035] FCP 112 is in direct contact and in close proximity with upperhot plate 124. Thus, FCP 112 is at nearly the same temperature as upperhot plate 124. Depending on whether the upper hot (chill) plate isacting to heat or cool the wafer, the gas flowing through manifold 111will be heated or cooled to roughly the same temperature as the wafer.Furthermore, the gas also passes directly through passages in upper hotplate 124, thus further assuring that the gas temperature arrives at atemperature of SPC 100 very near to the temperature at or near thesurface of wafer 126. Because of the large temperature controlledsurface area used for gas transport, the relatively long presence timeof the gas in contact with temperature controlled elements, and thedirect passage of the gas through the temperature controlled elements,heat is efficiently transferred to the gas. In the fabrication of verysmall integrated circuits having, for example, line widths of 0.18microns and smaller, this is a distinct advantage over the prior art,because the precise control of the temperature at the surface of thewafer directly impacts the relative rates of the diffusion and reactionprocesses, and thus the line width of the integrated circuits.

[0036] FIGS. 6-8 are cross sections of SPC 100 in various stages ofoperation. FIG. 6 shows SPC 100 open with wafer 126 in an elevatedposition. Wafer 126 is inserted onto lift pin assembly 130, which is inthe up position. In FIG. 7, lift pin assembly 130 has lowered wafer 126onto proximity pins 133 on lower hot plate 132. Upper hot plate 124 isin an up position as are flow channel plate 112 and cover plate 110 ofmanifold 111. One or both of hot (chill) plates 124 and 134 may beactive in this stage in order to heat or cool wafer 126. In addition,the gas may be flowing or may be turned off. Note the gap between theupper hot plate 124 and wafer 126.

[0037] In FIG. 8, upper hot plate 124 has been lowered to the downposition such that upper proximity pins 125 are in contact with lowerhot plate 132. The temperature of wafer 126 may be controlled in manyways, and the temperature gradient within SPC 100 may also be adjustedby modulating hot plates 124 and 132 together or independently. Byactivating both the upper hot plate 124 and the lower hot plate 132, thegradient in SPC 100 is greatly minimized compared to prior art designsonly having a lower hotplate. Furthermore, with the use of extendingupper proximity pins 125, the distance between the upper and lower hotplates can be altered in process to provide maximum flexibility andadjustability to the temperature profile. The temperature schedules ofthe hot plates can also be programmed to individually vary with timeduring any given temperature cycle or profile. Generally speaking, theramp time to a given temperature can be cut in half with the dual hotplate design of the current invention, in comparison the prior artdesigns. The ramp rate can also be much more precisely controlledcompared to prior designs.

[0038] Furthermore, because the heat is applied to the wafer from bothsides, flatness variations (warping) are better accommodated than withprior designs such as that of FIGS. 1-3. For example, if the wafer iswarped such that the ends of the wafer are further from the lower hotplate 132 than the center portion of the wafer, those same ends will benearer to upper hot plate 124. The warp of a 200 mm wafer can be up toabout 75 microns. In other words, the reduced heat gradient between thelower and upper hot plates 124 and 132 minimizes the temperaturedifference that imperfect wafers would otherwise be subjected to. This,intern, leads to more precise integrated circuit formation.

[0039] Gas can be applied to the wafer with upper hot plate 124 in theup or down position as seen in FIGS. 7 and 8. Also, in the crosssections of FIGS. 6-8, the gas passages 127 through upper hot plate 124may be seen. As the gas flows through manifold 111 and gas passages 127it is heated to the temperature of the upper hot plate 124. As mentionedpreviously, the temperature of upper hot plate 124 may be independentlymanipulated. Thus, the temperature of the gas distributed may also beheated or cooled to be at a selected temperature in order to produce adesired effect. The relatively long residual time of the gas and thelarge surface area of the heat transfer elements increases the precisiontemperature control of the gas, and thus the wafer, in comparison withprior art designs. In addition the control afforded by the laminar flowchannels that are dispersed to provide even flow about the surface ofthe wafer yields better control of the temperature within SPC 100.

[0040] The precise temperature control and fast dynamic response of SPC100 are assets in many operations. In particular, SPC 100 can bettercontrol the important transitions of chemically amplified resists. Asmentioned previously, chemically amplified resists require differingthermal profiles and energies to activate diffusion, the amplificationreaction, and the acid loss reaction. Thus precise temperature controlis of the utmost importance so that any reaction is not inadvertentlystarted or affected. Because the photogenerated acid diffuses throughthe resist as it catalyzes the deblocking reaction, the acid mayotherwise diffuse into unexposed regions and have a significant impacton the quality of the image generated in the resist. An importantcriteria of the post-exposure bake process (PEB) is optimization of thebalance between the relative rates of the diffusion and reactionprocesses. Because the diffusivity and the reaction rate are bothtemperature dependent, careful manipulation and monitoring of thethermal history of the resist is critical to the final dimensions of theintegrated circuit. The dual heating and cooling system and theprecision gas distribution system of the present invention make thispossible.

[0041] While embodiments of the present invention have been shown anddescribed, changes and modifications to these illustrative embodimentscan be made without departing from the present invention in its broaderaspects. Thus it should be evident that there are other embodiments ofthis invention which, while not expressly described above, are withinthe scope of the present invention. Therefore, it will be understoodthat the appended claims necessarily encompass all such changes andmodifications as fall within the described invention's true scope; andfurther that this scope is not limited merely to the illustrativeembodiments presented to demonstrate that scope.

1. A system for varying the temperature of a wafer comprising: a firsttemperature controlled plate; a second temperature controlled platecomprising proximity pins, the wafer located between the first andsecond temperature controlled plates and distanced from the secondtemperature controlled plate by the proximity pins; and an enclosuresurrounding the first and second temperature controlled plates and thewafer, the enclosure comprising a gas input and output, the gas flowingfrom the input past the wafer and to the output.
 2. The system of claim1 wherein the first temperature controlled plate further comprisesproximity pins, the proximity pins configured to distance the wafer fromthe first temperature controlled plate.
 3. The system of claim 2 whereinthe proximity pins are moveable such that the distance of the first andsecond temperature controlled plate from the wafer may be varied.
 4. Thesystem of claim 1 further comprising a flow distribution manifoldconfigured to distribute the gas upon the wafer.
 5. The system of claim4 wherein the flow distribution manifold comprises laminar flow paths,each laminar flow path comprising a laminar flow element controlling theflow rate of said flow path.
 6. The system of claim 5 wherein thelaminar flow element comprises a channel formed in a substrate.
 7. Thesystem of claim 5 wherein each of the laminar flow paths furthercomprise a cavity such that any contaminants or solvents that may bepresent in the enclosure and that may enter the flow paths willaccumulate in the cavity rather than in the laminar flow elements. 8.The system of claim 4 wherein the flow distribution manifold is incontact with the first temperature controlled plate, and wherein the gasdistributed is at substantially the same temperature as the firsttemperature controlled plate.
 9. The system of claim 8 wherein the firsttemperature control plate comprises flow channels and wherein the gasflows from the manifold and through the channels to the wafer.
 10. Thesystem of claim 1 further comprising a gas output flow regulator.
 11. Adevice for controlling the temperature of a wafer comprising: atemperature control element; and a gas distribution system configured todistribute gas at different points about a surface of the wafer, the gasdistribution system comprising a plurality of flow paths, each of theplurality of flow paths comprising a laminar flow element, wherein thewafer is located between the gas distribution system and the temperaturecontrol element.
 12. The device of claim 11 wherein the gas distributionsystem is temperature controlled thereby providing substantially uniformtemperature distribution and gas flow distribution across the surface ofthe wafer.
 13. The device of claim 11 further comprising an exhaustsystem configured to regulate the exhaust flow rate of the gas.
 14. Thedevice of claim 11 wherein the gas distribution system comprises one ormore heating and cooling elements.
 15. The device of claim 12 whereinthe gas distribution system and the temperature control element can beadjusted to different temperatures in order to vary the temperaturegradient within the device.
 16. A method of conditioning a wafer havinga first and a second side within a chamber, the method comprising:heating or cooling the wafer from the first side; heating or cooling thewafer from the second side; applying gas to the first side of the wafer,the gas distributed through a plurality of passages such that the gasflow is substantially laminar.
 17. The method of claim 16 furthercomprising heating or cooling the gas such that the gas is heated orcooled to substantially the same temperature as the first side of thewafer.
 18. A post exposure bake chamber comprising: a first heatingplate; a second heating plate; the first and second heating platesconfigured to heat a wafer placed between the plates, the wafer spacedfrom the first and second heating plates by proximity pins.
 19. The postexposure bake chamber of claim 18 further comprising a flow controlsystem having distributed gas flow paths and one or more flow controlelements regulating the gas flow rate through the gas flow paths. 20.The post exposure bake chamber of claim 19 wherein the flow controlsystem is in contact with the first heating plate such that the gas isheated by the first heating plate.
 21. The post exposure bake chamber ofclaim 19 wherein the gas passes from the flow control system throughpassages in the first heating plate to the wafer.
 22. The post exposurebake chamber of claim 19 wherein the flow control system comprises aflow channel plate, the one or more flow control elements formed in theflow channel plate.
 23. A wafer conditioning chamber comprising: a firstmeans for changing the temperature of the wafer at a first side of thewafer; a second means for changing the temperature of the wafer at asecond side of the wafer; and a gas distribution means for distributinga gas at a controlled flow rate at a plurality of locations upon thefirst or second side of the wafer.
 24. The wafer conditioning chamber ofclaim 23 wherein the gas temperature is manipulated by the first orsecond means for changing the temperature of the wafer.
 25. The waferconditioning chamber of claim 24 wherein the gas distribution meanscomprises flow control means for controlling the flow rate of the gas.